Pillar-shaped semiconductor memory device and method for producing the same

ABSTRACT

A pillar-shaped semiconductor memory device includes an i-layer substrate and silicon pillars formed on the i-layer substrate. Tunnel insulating layers, a data charge storage insulating layer, an interlayer insulating layer, and gas layers are formed so as to surround outer peripheries of the silicon pillars. Word lines that are separated from each other by interlayer insulating layers are formed so as to surround outer peripheries of the gas layers in a direction perpendicular to an upper surface of the i-layer substrate.

CROSS REFERENCES TO RELATED APPLICATION

The present application is a continuation application of PCT/JP2014/055499, filed Mar. 4, 2014, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a pillar-shaped semiconductor memory device which is a memory device formed in a pillar-shaped semiconductor, and a method for producing the device.

2. Description of the Related Art

In recent years, electronic devices using a memory device typified by a flash memory have been used in various fields, and the market size and application fields of the devices have been further expanding. With these circumstances, the realization of highly integrated memory devices and a reduction in the cost of the memory devices have been desired.

NAND-type flash memories (refer to, for example, C. Y. Ting, V. J. Vivalda, and H. G. Schaefer: “Study of planarized sputter-deposited SiO₂”, J. Vac. Sci. Technol. 15(3), p.p. 1105-1112, May/June (1978)) are advantageous in the realization of highly integrated devices and a reduction in the cost of the devices. Vertical NAND-type flash memories in which a plurality of memory cell-transistors are stacked around a semiconductor silicon pillar (hereinafter, a semiconductor silicon pillar is referred to as “Si pillar”) realize more highly integrated devices (refer to, for example, Japanese Unexamined Patent Application Publication No. 4-79369).

FIG. 8 illustrates a sectional structure of an example of a vertical NAND-type flash memory in the related art (refer to, Japanese Unexamined Patent Application Publication No. 4-79369). Silicon (Si) pillars 101 a and 101 b are formed on an intrinsic semiconductor silicon substrate 100 (hereinafter, an intrinsic semiconductor silicon substrate is referred to as “i-layer substrate”). Silicon dioxide (SiO₂) layers 102 a and 102 b which are tunnel insulating layers are formed so as to surround outer peripheries of the Si pillars 101 a and 101 b, respectively. Floating electrodes 103 a and 103 b that electrically float are formed so as to surround outer peripheries of the SiO₂ layers 102 a and 102 b, respectively. Source-side selection gate electrodes 104 a and 104 b are formed around lower portions of the Si pillars 101 a and 101 b, respectively. Drain-side selection gate electrodes 105 a and 105 b are formed around upper portions of the Si pillars 101 a and 101 b, respectively. Interlayer SiO₂ layers 107 a and 107 b are formed so as to surround outer peripheries of the floating electrodes 103 a and 103 b, respectively. Word-line electrodes 108 a and 108 b are formed so as to surround outer peripheries of the interlayer SiO₂ layers 107 a and 107 b, respectively. A common source N⁺ layer 109 (hereinafter, a semiconductor layer containing a donor impurity in a large amount is referred to as “N⁺ layer”) is formed in a surface layer of the i-layer substrate 100, the surface layer being connected to bottom portions of the Si pillars 101 a and 101 b. Drain N⁺ layers 110 a and 110 b are formed in top portions of the Si pillars 101 a and 101 b, respectively. A SiO₂ layer 111 is further formed by chemical vapor deposition (CVD) so as to cover the whole. Bit-line wiring metal layers 113 a and 113 b are respectively formed through contact holes 112 a and 112 b formed on the drain N⁺ layers 110 a and 110 b. Furthermore, P⁻ layers 114 a and 114 b (hereinafter, a semiconductor layer containing an acceptor impurity in a small amount is referred to as “P⁻ layer”) are respectively formed in the Si pillars 101 a and 101 b on the i-layer substrate 100. Memory cell-transistors Qc1 including the SiO₂ layers 102 a and 102 b, the floating electrodes 103 a and 103 b, the interlayer SiO₂ layers 107 a and 107 b, and the word-line electrodes 108 a and 108 b are respectively formed on the source-side selection gate electrodes 104 a and 104 b of the Si pillars 101 a and 101 b so as to surround outer peripheries of the P⁻ layers 114 a and 114 b. Memory cell-transistors Qc2 and Qc3 that have the same structure as the memory cell-transistor Qc1 and that are electrically separated from each other are formed on the memory cell-transistor Qc1. Furthermore, source-side selection transistors Qs1 having the source-side selection gate electrodes 104 a and 104 b are formed below the memory cell-transistors Qc1, Qc2, and Qc3. Drain-side selection transistors Qs2 having the drain-side selection gate electrodes 105 a and 105 b are formed above the memory cell-transistors Qc1, Qc2, and Qc3. With this structure, a vertical NAND-type flash memory element having a high density is formed.

In the vertical NAND-type flash memory element illustrated in FIG. 8, it is desirable to easily form the SiO₂ layers 102 a and 102 b which are tunnel insulating layers, the interlayer SiO₂ layers 107 a and 107 b, the source-side selection gate electrodes 104 a and 104 b, the drain-side selection gate electrodes 105 a and 105 b, the floating electrodes 103 a and 103 b, and the word-line electrodes 108 a and 108 b, all of which have less defects and high reliability so as to surround outer peripheral portions of the Si pillars 101 a and 101 b, respectively.

A known vertical NAND-type flash memory is produced by repeatedly stacking word-line electrode material layers and insulation films in a vertical direction, subsequently forming a through-hole passing through the stacked word-line electrode material layers and the insulation films, subsequently forming an interlayer insulation film, a Si₃N₄ layer (silicon nitride layer) that stores data charges, and a tunnel SiO₂ layer on a surface layer of a side face of the through-hole, and further filling the through-hole with a poly-Si layer (hereinafter, a polycrystalline Si layer is referred to as “poly-Si layer”) which is to become a channel (refer to, for example, the specification of U. S. Patent Application Publication No. 2007/0252201). Also in this vertical NAND-type flash memory, it is desirable to easily form the interlayer insulation film, the Si₃N₄ layer, the tunnel SiO₂ layer, and the word-line electrodes, all of which have less defects and high reliability.

In the vertical NAND-type flash memory illustrated in FIG. 8, it is desirable to easily form the SiO₂ layers 102 a and 102 b, the interlayer SiO₂ layers 107 a and 107 b, the source-side selection gate electrodes 104 a and 104 b, the drain-side selection gate electrodes 105 a and 105 b, the floating electrodes 103 a and 103 b, and the word-line electrodes 108 a and 108 b, all of which have less defects and high reliability so as to surround outer peripheral portions of the Si pillars 101 a and 101 b.

SUMMARY OF THE INVENTION

A pillar-shaped semiconductor memory device according to a first aspect of the present invention includes a semiconductor substrate; a first semiconductor pillar disposed on the semiconductor substrate and extending in a direction perpendicular to a surface of the semiconductor substrate; a tunnel insulating layer surrounding an outer periphery of the first semiconductor pillar; a data charge storage insulating layer surrounding an outer periphery of the tunnel insulating layer; a first interlayer insulating layer surrounding an outer periphery of the data charge storage insulating layer; a space surrounding an outer periphery of the first interlayer insulating layer; at least one stacked material layer that surrounds an outer periphery of the space and that is formed in a direction perpendicular to the surface of the semiconductor substrate, the stacked material layer including a first conductor layer and a second interlayer insulating layer; and a second conductor layer that is formed on the outer periphery of the first semiconductor pillar and on the at least one stacked material layer, that supports a side face of the first interlayer insulating layer, and that seals the space. In the pillar-shaped semiconductor memory device, the first interlayer insulating layer and the space insulate the first conductor layer from the data charge storage insulating layer. The first interlayer insulating layer insulates the second conductor layer from the data charge storage insulating layer. Data writing and erasing due to data charge transfer between the first semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer or data charge retention by the data charge storage insulating layer is performed by application of a voltage to the first conductor layer.

The at least one stacked material layer preferably includes a plurality of stacked material layers. The pillar-shaped semiconductor memory device preferably further includes a first gate insulating layer formed below the stacked material layers and surrounding the outer periphery of the first semiconductor pillar, a third conductor layer surrounding an outer periphery of the first gate insulating layer, a first impurity region formed below the third conductor layer and in a bottom portion of the first semiconductor pillar and containing a donor or acceptor impurity, a second gate insulating layer formed above the stacked material layers and surrounding the outer periphery of the first semiconductor pillar, a fourth conductor layer surrounding an outer periphery of the second gate insulating layer, and a second impurity region formed in a top portion of the first semiconductor pillar and having the same conductivity type as the first impurity region. Preferably, the first conductor layer of each of the stacked material layers is connected to a word-line wiring metal layer, the third conductor layer is connected to a source-side selection gate wiring metal layer, the first impurity region is connected to a common source wiring metal layer, the fourth conductor layer is connected to a drain-side selection gate wiring metal layer, and the second impurity region is connected to a bit-line wiring metal layer to form a NAND-type flash memory element in the first semiconductor pillar.

An outer peripheral edge of the first semiconductor pillar is preferably disposed inside an outer peripheral edge of the space in plan view.

The pillar-shaped semiconductor memory device preferably further includes a first outer peripheral semiconductor region formed in an outer periphery of a memory element region in which the first semiconductor pillar is formed; a second semiconductor pillar which is formed in a second outer peripheral semiconductor region included in the first outer peripheral semiconductor region, whose top portion has a height substantially equal to that of a top portion of the first semiconductor pillar, and whose bottom surface has a height substantially equal to that of a bottom surface of the fourth conductor layer; a third gate insulating layer surrounding an outer periphery of the second semiconductor pillar; a fifth conductor layer which is formed so as to surround an outer periphery of the third gate insulating layer, and whose upper and lower ends have heights substantially equal to those of upper and lower ends of the fourth conductor layer; a third impurity region formed above the fifth conductor layer and in a top portion of the second semiconductor pillar and containing a donor or acceptor impurity; and a fourth impurity region formed below the fifth conductor layer and in a bottom portion of the second semiconductor pillar and having the same conductivity type as the third impurity region. A surrounding gate MOS transistor (SGT) is preferably formed in which when one of the third impurity region and the fourth impurity region functions as a source, the other functions as a drain, the second semiconductor pillar disposed between the third impurity region and the fourth impurity region functions as a channel, and the fifth conductor layer functions as a gate.

The pillar-shaped semiconductor memory device preferably further includes a third interlayer insulating layer that is formed on the semiconductor substrate so as to surround the outer periphery of the first semiconductor pillar, and that extends to a side face and an upper surface of the first outer peripheral semiconductor region; and a contact hole connected to an upper surface of the first conductor layer of one of the stacked material layers that have an upper surface on an upper end of a side face of the first outer peripheral semiconductor region. The stacked material layers are preferably formed on the third interlayer insulating layer. An upper surface of the stacked material layers preferably has a height substantially equal to that of an upper surface of the third interlayer insulating layer located on the first outer peripheral semiconductor region. The first conductor layer and the word-line wiring metal layer are preferably connected to each other through the contact hole.

A method for producing a pillar-shaped semiconductor memory device according to a second aspect of the present invention includes a mask insulating layer-forming step of forming, on a semiconductor substrate, a mask insulating layer having a circular shape in plan view; a first semiconductor pillar-forming step of forming a first semiconductor pillar by etching the semiconductor substrate using the mask insulating layer as a mask to form a semiconductor pillar on the semiconductor substrate, and retracting a side face of the semiconductor pillar to the inside of the semiconductor pillar; a tunnel insulating layer-forming step of forming a tunnel insulating layer so as to surround an outer periphery of the first semiconductor pillar; a data charge storage insulating layer-forming step of forming a data charge storage insulating layer so as to surround an outer periphery of the tunnel insulating layer; a first interlayer insulating layer-forming step of forming a first interlayer insulating layer so as to surround an outer periphery of the data charge storage insulating layer; a first conductor layer-forming step of forming a first conductor layer on the outer periphery of the first semiconductor pillar and above the semiconductor substrate by allowing a material atom to be incident from a direction perpendicular to an upper surface of the mask insulating layer; a second interlayer insulating layer-forming step of forming a second interlayer insulating layer by allowing a material atom to be incident on the first conductor layer from a direction perpendicular to the upper surface of the mask insulating layer; a space-forming step of forming a space between a side face of the first interlayer insulating layer and side faces of the first conductor layer and the second interlayer insulating layer in parallel with the first conductor layer-forming step and the second interlayer insulating layer-forming step; and a stacked material layer-forming step of forming at least one stacked material layer in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer as one set. In the method, data writing and erasing due to data charge transfer between the first semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer or data charge retention by the data charge storage insulating layer is performed by application of a voltage to the first conductor layer.

The method preferably further includes a second conductor layer-forming step of forming a second conductor layer on the outer periphery of the first semiconductor pillar and on the at least one stacked material layer by allowing a material atom to be incident from a direction perpendicular to the upper surface of the mask insulating layer; and a second conductor layer-first interlayer insulating layer-connecting step of connecting the second conductor layer to the first interlayer insulating layer by expanding the second conductor layer by heat treatment in a direction parallel to the upper surface of the semiconductor substrate.

In the method, between the stacked material layer-forming step and the second conductor layer-first interlayer insulating layer-connecting step, heat treatment is preferably performed in an atmosphere containing hydrogen.

In the method, between the stacked material layer-forming step and the second conductor layer-first interlayer insulating layer-connecting step, heat treatment is preferably performed in an atmosphere containing oxygen to form an oxide insulating layer in a surface layer of a side face of the first conductor layer.

The method preferably includes a truncated cone-shaped mask insulating layer-forming step of forming, as the mask insulating layer, a truncated cone-shaped mask insulating layer having a truncated cone shape on the first semiconductor pillar; and a cone-shaped stacked material layer-forming step of depositing a material atom by allowing the material atom to be incident from a direction perpendicular to the upper surface of the semiconductor substrate under a condition in which a deposition rate of the material atom on a side face of the truncated cone-shaped mask insulating layer is lower than a removal rate of the material atom to form the at least one stacked material layer above the semiconductor substrate and to form, on the truncated cone-shaped mask insulating layer, a cone-shaped stacked material layer having a conical shape and formed of a material layer common to the at least one stacked material layer.

The method preferably further includes a first gate insulating layer-forming step of forming a first gate insulating layer below the at least one stacked material layer so as to surround the outer periphery of the first semiconductor pillar; a third conductor layer-forming step of forming a third conductor layer so as to surround an outer periphery of the first gate insulating layer; a first impurity region-forming step of forming a first impurity region below the third conductor layer and in a bottom portion of the first semiconductor pillar, the first impurity region containing a donor or acceptor impurity; a second gate insulating layer-forming step of forming a second gate insulating layer above the at least one stacked material layer so as to surround the outer periphery of the first semiconductor pillar; a fourth conductor layer-forming step of forming a fourth conductor layer so as to surround an outer periphery of the second gate insulating layer; and a second impurity region-forming step of forming a second impurity region above the fourth conductor layer, the second impurity region having the same conductivity type as the first impurity region. Preferably, the first conductor layer of the at least one stacked material layer is connected to a word-line wiring metal layer, the third conductor layer is connected to a source-side selection gate wiring metal layer, the first impurity region is connected to a common source wiring metal layer, the fourth conductor layer is connected to a drain-side selection gate wiring metal layer, and the second impurity region is connected to a bit-line wiring metal layer to form a NAND-type flash memory element in the first semiconductor pillar.

The method preferably further includes a first outer peripheral semiconductor region-forming step of forming a first outer peripheral semiconductor region in an outer periphery of a memory element region in which the first semiconductor pillar is formed; a second semiconductor pillar-forming step of forming, in a second outer peripheral semiconductor region included in the first outer peripheral semiconductor region, a second semiconductor pillar whose top portion has a height substantially equal to that of a top portion of the first semiconductor pillar, and whose bottom surface has a height substantially equal to that of a bottom surface of the fourth conductor layer; a third gate insulating layer-forming step of forming a third gate insulating layer so as to surround an outer periphery of the second semiconductor pillar; a fifth conductor layer-forming step of forming a fifth conductor layer whose upper and lower ends have heights substantially equal to those of upper and lower ends of the fourth conductor layer in a direction perpendicular to the semiconductor substrate so as to surround an outer periphery of the third gate insulating layer; a third impurity region-forming step of forming a third impurity region above the fifth conductor layer and in a top portion of the second semiconductor pillar, the third impurity region containing a donor or acceptor impurity; and a fourth impurity region-forming step of forming a fourth impurity region below the fifth conductor layer and in a bottom portion of the second semiconductor pillar, the fourth impurity region having the same conductivity type as the third impurity region. A surrounding gate MOS transistor (SGT) is preferably formed in which when one of the third impurity region and the fourth impurity region functions as a source, the other functions as a drain, the second semiconductor pillar disposed between the third impurity region and the fourth impurity region functions as a channel, and the fifth conductor layer function as a gate.

The method preferably further includes a third interlayer insulating layer-forming step of forming a third interlayer insulating layer on the semiconductor substrate so as to surround the outer periphery of the first semiconductor pillar, the third interlayer insulating layer extending to a side face and an upper surface of the first outer peripheral semiconductor region; and a contact hole-forming step of forming a contact hole so as to be connected to an upper surface of the first conductor layer of the at least one stacked material layer that has an upper surface on an upper end of a side face of the second outer peripheral semiconductor region. The at least one stacked material layer is preferably formed on the third interlayer insulating layer. An upper surface of the at least one stacked material layer preferably has a height substantially equal to that of an upper surface of the third interlayer insulating layer located on the first outer peripheral semiconductor region. The first conductor layer and the word-line wiring metal layer are preferably connected to each other through the contact hole.

According to the aspects of the present invention, a pillar-shaped semiconductor memory device having high reliability and a high density can be provided at a low cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a vertical NAND-type flash memory device according to a first embodiment of the present invention.

FIG. 2AA and FIGS. 2AB and 2AC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2BA and FIGS. 2BB and 2BC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2CA and FIGS. 2CB and 2CC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2DA and FIGS. 2DB and 2DC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2EA and FIGS. 2EB and 2EC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2FA and FIGS. 2FB and 2FC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2GA and FIGS. 2GB and 2GC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2HA and FIGS. 2HB and 2HC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2IA and FIGS. 2IB and 2IC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2JA and FIGS. 2JB and 2JC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 2KA and FIGS. 2KB and 2KC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the first embodiment and a method for producing the device.

FIG. 3A and FIGS. 3B and 3C are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to a second embodiment of the present invention and a method for producing the device.

FIG. 4AA and FIGS. 4AB and 4AC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to a third embodiment of the present invention and a method for producing the device.

FIG. 4BA and FIGS. 4BB and 4BC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the third embodiment and a method for producing the device.

FIGS. 5AA to 5AD are views illustrating a deposited shape when material atoms are deposited on a pillar having a trapezoidal cross section and formed on a substrate by using a bias sputtering method, according to a fourth embodiment of the present invention.

FIG. 5BA and FIGS. 5BB and 5BC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the fourth embodiment and a method for producing the device.

FIG. 5CA and FIGS. 5CB and 5CC are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to the fourth embodiment and a method for producing the device.

FIG. 6A and FIGS. 6B and 6C are respectively a plan view and sectional structural views illustrating a vertical NAND-type flash memory device according to a fifth embodiment of the present invention and a method for producing the device.

FIG. 7AA and FIG. 7AB are respectively a plan view and a sectional structural view illustrating a vertical NAND-type flash memory device according to a sixth embodiment of the present invention and a method for producing the device.

FIG. 7BA and FIG. 7BB are respectively a plan view and a sectional structural view illustrating a vertical NAND-type flash memory device according to the sixth embodiment and a method for producing the device.

FIG. 7CA and FIG. 7CB are respectively a plan view and a sectional structural view illustrating a vertical NAND-type flash memory device according to the sixth embodiment and a method for producing the device.

FIG. 7DA and FIG. 7DB are respectively a plan view and a sectional structural view illustrating a vertical NAND-type flash memory device according to the sixth embodiment and a method for producing the device.

FIG. 7EA and FIG. 7EB are respectively a plan view and a sectional structural view illustrating a vertical NAND-type flash memory device according to the sixth embodiment and a method for producing the device.

FIG. 7FA and FIG. 7FB are respectively a plan view and a sectional structural view illustrating a vertical NAND-type flash memory device according to the sixth embodiment and a method for producing the device.

FIG. 7GA and FIG. 7GB are respectively a plan view and a sectional structural view illustrating a vertical NAND-type flash memory device according to the sixth embodiment and a method for producing the device.

FIG. 7HA and FIG. 7HB are respectively a plan view and a sectional structural view illustrating a vertical NAND-type flash memory device according to the sixth embodiment and a method for producing the device.

FIG. 8 is a sectional structural view of an example of a vertical NAND-type flash memory device in the related art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Vertical (pillar structure) NAND-type flash memory devices according to embodiments of the present invention, and methods for producing the devices will now be described with reference to the drawings.

First Embodiment

A method for producing a vertical NAND-type flash memory device according to a first embodiment of the present invention will be described with reference to FIG. 1 and FIGS. 2AA to 2KC.

FIG. 1 illustrates a NAND-type flash memory circuit according to a first embodiment. Gate electrodes of memory cell-transistors WT11, WT12, and WT1 n, the number of which is n, and which are connected in series are respectively connected to word lines W1, W2, and Wn, the number of which is n. A source-side selection transistor STS1 and a drain-side selection transistor STD1 are connected to both sides of the memory cell-transistors WT11, WT12, and WT1 n, the number of which is n. A gate electrode of the source-side selection transistor STS1 is connected to a source-side selection line SGS. A gate electrode of the drain-side selection transistor STD1 is connected to a drain-side selection line SGD. A source of the source-side selection transistor STS1 is connected to a common source line CSL. A drain of the drain-side selection transistor STD1 is connected to a bit line BL1. Memory cell-transistors WT21, WT22, and WT2 n, the number of which is n, and which are connected in series are formed in parallel with the memory cell-transistors WT11, WT12, and WT1 n, the number of which is n, and which are connected in series. Gate electrodes of the memory cell-transistors WT21, WT22, and WT2 n, the number of which is n are respectively connected to the word lines W1, W2, and Wn. A source-side selection transistor STS2 and a drain-side selection transistor STD2 are respectively connected to the lower side and the upper side of the memory cell-transistors WT21, WT22, and WT2 n. A gate electrode of the source-side selection transistor STS2 is connected to the source-side selection line SGS. A gate electrode of the drain-side selection transistor STD2 is connected to the drain-side selection line SGD. A source of the source-side selection transistor STS2 is connected to the common source line CSL. A drain of the drain-side selection transistor STD2 is connected to a bit line BL2. The structure including this circuit is repeatedly formed in a block memory element region.

A method for producing a pillar-shaped semiconductor memory device according to the first embodiment will now be described with reference to FIGS. 2AA to 2KC. In FIGS. 2AA to 2KC, the drawings whose last reference character is A are plan views, the drawings whose last reference character is B are sectional views taken along line X-X′ in the drawings whose last reference character is A, and the drawings whose last reference character is C are sectional views taken along line Y-Y′ in the drawings whose last reference character is A.

As illustrated in FIGS. 2AA to 2AC, a Si₃N₄ film (not shown) is formed on an i-layer substrate 1. A resist film (not shown) is applied onto the Si₃N₄ film. Resist layers 3 a, 3 b, 3 c, and 3 d each having a circular shape in plan view are formed by a lithographic method. Next, the Si₃N₄ film is etched by, for example, a reactive ion etching (RIE) method using the resist layers 3 a, 3 b, 3 c, and 3 d as a mask to form Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d, respectively.

Next, as illustrated in FIGS. 2BA to 2BC, the i-layer substrate 1 is etched by, for example, an RIE method using the resist layers 3 a, 3 b, 3 c, and 3 d and the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d to form Si pillars 4 a, 4 b, 4 c, and 4 d, respectively. The resist layers 3 a, 3 b, 3 c, and 3 d are then removed.

Next, as illustrated in FIGS. 2CA to 2CC, for example, an arsenic (As) ion is implanted into a surface layer of an i-layer substrate 1 a disposed on outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d to form an N⁺ layer 5. A SiO₂ layer 9 is formed on the i-layer substrate 1 a disposed on the outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d. Furthermore, SiO₂ layers 6 a, 6 b, 6 c, and 6 d (the SiO₂ layer 6 c is not shown in the figures) are formed by, for example, a thermal oxidation method in surface layers of side faces of the Si pillars 4 a, 4 b, 4 c, and 4 d. Subsequently, a doped Si layer 7 (hereinafter, a poly-Si layer containing an acceptor or donor impurity is referred to as “doped Si layer”) is formed on the SiO₂ layer 9 disposed on the outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d. Subsequently, a Si₃N₄ layer 8 is formed on the doped Si layer 7.

Next, as illustrated in FIGS. 2DA to 2DC, SiO₂ layers 10 a, 10 b, 10 c, and 10 d (the SiO₂ layer 10 c is not shown in the figures) are formed by a thermal oxidation method so as to have a large thickness in surface layers of side faces of the Si pillars 4 a, 4 b, 4 c, and 4 d using the Si₃N₄ layers 2 a, 2 b, 2 c, 2 d, and 8 as a mask. Subsequently, the SiO₂ layers 10 a, 10 b, 10 c, and 10 d are removed. The Si₃N₄ layers 2 a, 2 b, 2 c, 2 d, and 8 are not oxidized by the thermal oxidation method. Therefore, when the SiO₂ layers 10 a, 10 b, 10 c, and 10 d are removed, the diameter of a cross section of each of the Si pillars 4 a, 4 b, 4 c, and 4 d becomes smaller than the diameter of a cross section of each of the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d.

Next, as illustrated in FIGS. 2EA to 2EC, SiO₂ layers 11 a, 11 b, 11 c, and 11 d (the SiO₂ layer 11 c is not shown in the figures) which are to become tunnel insulating layers are formed by, for example, a thermal oxidation method in surface layers of the side faces of the Si pillars 4 a, 4 b, 4 c, and 4 d. Subsequently, a Si₃N₄ layer 12 which is to become a data charge storage insulating layer and a SiO₂ layer 13 which is to become an interlayer insulating layer are formed so as to cover the whole.

Next, as illustrated in FIGS. 2FA to 2FC, a Si material that contains a donor or acceptor impurity and a SiO₂ material are incident from a direction perpendicular to a surface of the i-layer substrate 1 a by using, for example, a bias sputtering method to form doped Si layers 14 a 1, 14 a 2, and 14 an and SiO₂ layers 15 a 1, 15 a 2, and 15 an on outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d. In this embodiment, doped Si layers 14 b 1, 14 b 2, 14 bn, 14 c 1, 14 c 2, 14 cn, 14 d 1, 14 d 2, 14 dn, 14 e 1, 14 e 2, and 14 en (the doped Si layers 14 d 1, 14 d 2, and 14 dn are not shown in the figures) and SiO₂ layers 15 b 1, 15 b 2, 15 bn, 15 c 1, 15 c 2, 15 cn, 15 d 1, 15 d 2, 15 dn, 15 e 1, 15 e 2, and 15 en (the SiO₂ layers 15 d 1, 15 d 2, and 15 dn are not shown in the figure) are stacked on the Si pillars 4 a, 4 b, 4 c, and 4 d. Subsequently, a TiN (titanium nitride) layer 16 a and a SiO₂ layer 17 a are similarly formed on the outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d by using, for example, a bias sputtering method. At the same time, TiN layers 16 b, 16 c, 16 d, and 16 e (the TiN layer 16 d is not shown in the figures), and SiO₂ layers 17 b, 17 c, 17 d, and 17 e (the SiO₂ layer 17 d is not shown in the figure) are stacked on the Si pillars 4 a, 4 b, 4 c, and 4 d, respectively. As described above, the Si material that contains a donor or acceptor impurity and the SiO₂ material are incident from a direction perpendicular to a surface of the i-layer substrate 1 a. Therefore, the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d function as a mask, and gas layers (spaces, for example, air layers containing air) 18 a, 18 b, 18 c, and 18 d (the gas layer 18 c is not shown in the figures) are formed between the side faces of the SiO₂ layer 13 formed on the side faces of the Si pillars 4 a, 4 b, 4 c, and 4 d and the side faces of the doped Si layers 14 a 1, 14 a 2, and 14 an and the SiO₂ layers 15 a 1, 15 a 2, and 15 an.

Next, as illustrated in FIGS. 2GA to 2GC, heat treatment is performed at, for example, 550° C. In this step, the SiO₂ layer 17 a is used as a cap, and the TiN layer 16 a is plastically deformed to extend in the horizontal direction of FIG. 2GB. Thus, a TiN layer 16 aa that contacts the SiO₂ layer 13 is formed. Consequently, gaps of the top portions of the gas layers (spaces) 18 a, 18 b, 18 c, and 18 d are sealed with the TiN layer 16 aa. Similarly, the TiN layers 16 b, 16 c, 16 d, and 16 e on the Si pillars 4 a, 4 b, 4 c, and 4 d are also plastically deformed using the SiO₂ layers 17 b, 17 c, 17 d, and 17 e as a cap, respectively, to extend in the horizontal direction of FIG. 2GB. Thus, TiN layers 16 bb, 16 cc, 16 dd, and 16 ee (the TiN layer 16 dd is not shown in the figures) are formed.

Next, as illustrated in FIGS. 2HA to 2HC, the doped Si layers 14 b 1, 14 b 2, 14 bn, 14 c 1, 14 c 2, 14 cn, 14 d 1, 14 d 2, 14 dn, 14 e 1, 14 e 2, and 14 en, the SiO₂ layers 15 b 1, 15 b 2, 15 bn, 15 c 1, 15 c 2, 15 cn, 15 d 1, 15 d 2, 15 dn, 15 e 1, 15 e 2, and 15 en, the TiN layers 16 bb, 16 cc, 16 dd, and 16 ee, and the SiO₂ layers 17 b, 17 c, 17 d, and 17 e on the Si pillars 4 a, 4 b, 4 c, and 4 d are removed. Subsequently, the SiO₂ layers 11 a, 11 b, 11 c, and 11 d, the Si₃N₄ layer 12, and the SiO₂ layer 13 that are disposed above the upper surface of the TiN layer 16 aa and cover the Si pillars 4 a, 4 b, 4 c, and 4 d are removed to form SiO₂ layers 11 aa, 11 bb, 11 cc, and 11 dd (the SiO₂ layer 11 cc is not shown in the figures), a Si₃N₄ layer 12 a, and a SiO₂ layer 13 a. Subsequently, the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d are removed.

Next, as illustrated in FIGS. 2IA to 2IC, a hafnium oxide layer (hereinafter, a hafnium oxide layer is referred to as “HfO₂ layer”) 19 is formed so as to cover the TiN layer 16 aa and exposed top portions of the Si pillars 4 a, 4 b, 4 c, and 4 d. Subsequently, a doped Si layer 20 and a SiO₂ layer 21 are formed by using, for example, a bias sputtering method. The doped Si layer 20 and SiO₂ layer 21 that are formed on the top portions of the Si pillars 4 a, 4 b, 4 c, and 4 d are then removed (the removal step is not shown). Furthermore, the HfO₂ layer 19 disposed on the top portions of the Si pillars 4 a, 4 b, 4 c, and 4 d is removed. Subsequently, N⁺ layers 24 a, 24 b, 24 c, and 24 d (the N⁺ layer 24 c is not shown in the figures) are formed in the top portions of the Si pillars 4 a, 4 b, 4 c, and 4 d by, for example, an arsenic (As) ion implantation method.

Next, as illustrated in FIGS. 2JA to 2JC, resist layers 26 a and 26 b that cover the Si pillars 4 a, 4 b, 4 c, and 4 d and that extend in the horizontal direction as illustrated in FIG. 2JA are formed. The resist layer 26 a covers the Si pillars 4 a and 4 b and extends in the horizontal direction as illustrated in FIG. 2JA. The resist layer 26 b covers the Si pillars 4 c and 4 d and extends in the horizontal direction as illustrated in FIG. 2JA. Subsequently, the SiO₂ layer 21 and the doped Si layer 20 are etched from the upper surface thereof by RIE using the resist layers 26 a and 26 b as a mask. As a result, a SiO₂ layer 21 a and a doped Si layer 20 a are formed under the resist layer 26 a. At the same time, a SiO₂ layer 21 b and a doped Si layer 20 b are formed under the resist layer 26 b. The resist layers 26 a and 26 b are then removed.

Next, as illustrated in FIGS. 2KA to 2KC, a SiO₂ layer 28 is deposited by a chemical vapor deposition (CVD) method over the entire surface, and contact holes 29 a, 29 b, 29 c, and 29 d are formed on the Si pillars 4 a, 4 b, 4 c, and 4 d, respectively. Subsequently, metal wiring layers 30 a and 30 b that are connected to the N⁺ layers 24 a, 24 b, 24 c, and 24 d through the contact holes 29 a, 29 b, 29 c, and 29 d are formed so as to extend in the vertical direction of the FIG. 2KA. The metal wiring layer 30 a is connected to the N⁺ layers 24 a and 24 c (the N⁺ layer 24 c is not shown in the figures) that are respectively formed on the Si pillars 4 a and 4 c. The metal wiring layer 30 b is connected to the N⁺ layers 24 b and 24 d that are respectively formed on the Si pillars 4 b and 4 d. A vertical NAND-type flash memory is formed as described above.

In FIGS. 2KA to 2KC, the N⁺ layer 5 a functions as a common source, the doped Si layer 7 functions as a source-side selection line, the doped Si layers 14 a 1, 14 a 2, and 14 an function as word lines, the doped Si layer 20 a functions as a drain-side selection line, the N⁺ layers 24 a, 24 b, 24 c, and 24 d function as drains, and the metal wiring layers 30 a and 30 b function as bit lines. The SiO₂ layers 11 aa, 11 bb, 11 cc, and 11 dd function as tunnel insulating layers. The Si₃N₄ layer 12 a functions as a data charge storage insulating layer. The SiO₂ layer 13 a functions as an interlayer insulating layer. During a data write operation and a data read-out operation, a voltage with which channels of the Si pillars 4 a, 4 b, 4 c, and 4 d turn to the on-state is preferably applied to the TiN layer 16 aa.

According to the first embodiment, the following advantages are achieved.

1. In the vertical NAND-type flash memory formed to have the structure illustrated in FIGS. 2KA to 2KC, a stacked insulating layer that is formed so as to surround the Si pillars 4 a, 4 b, 4 c, and 4 d and that includes the SiO₂ layers 11 aa, 11 bb, 11 cc, and 11 dd functioning as tunnel insulating layers, the Si₃N₄ layer 12 a functioning as a data charge storage insulating layer, and the SiO₂ layer 13 a functioning as an interlayer insulating layer is formed to be isolated from the doped Si layers 14 a 1, 14 a 2, and 14 an functioning as word lines and the SiO₂ layers 15 a 1, 15 a 2, and 15 an functioning as interlayer insulating layers with the gas layers 18 a, 18 b, 18 c, and 18 d therebetween. With this structure, the transfer of a stress from the doped Si layers 14 a 1, 14 a 2, and 14 an and the SiO₂ layers 15 a 1, 15 a 2, and 15 an to the SiO₂ layers 11 aa, 11 bb, 11 cc, and 11 dd, the Si₃N₄ layer 12 a, and the SiO₂ layer 13 a is blocked. As a result, the generation of defects in the SiO₂ layers 11 aa, 11 bb, 11 cc, and 11 dd, the Si₃N₄ layer 12 a, and the SiO₂ layer 13 a can be suppressed to improve reliability of memory characteristics.

2. As illustrated in FIGS. 2FA to 2FC, the SiO₂ layers 11 a, 11 b, 11 c, and 11 d functioning as tunnel insulating layers, the Si₃N₄ layer 12 functioning as a data charge storage insulating layer, and the SiO₂ layer 13 functioning as an interlayer insulating layer are formed so as to surround the Si pillars 4 a, 4 b, 4 c, and 4 d. Subsequently, a Si material that contains a donor or acceptor impurity and a SiO₂ material are incident from a direction perpendicular to a surface of the i-layer substrate 1 a by using a bias sputtering method to form the doped Si layers 14 a 1, 14 a 2, and 14 an and the SiO₂ layers 15 a 1, 15 a 2, and 15 an on outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d. In this case, since the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d function as a mask, atoms of the Si material that contains the donor or acceptor impurity and atoms of the SiO₂ material are not incident on the surface of the SiO₂ layer 13 disposed on the side faces of the Si pillars 4 a, 4 b, 4 c, and 4 d. Therefore, the SiO₂ layers 11 a, 11 b, 11 c, and 11 d functioning as tunnel insulating layers, the Si₃N₄ layer 12 functioning as a data charge storage insulating layer, and the SiO₂ layer 13 functioning as an interlayer insulating layer are not damaged by the incidence of atoms of the Si material and atoms of the SiO₂ material. As a result, the generation of defects in the SiO₂ layers 11 a, 11 b, 11 c, and 11 d, the Si₃N₄ layer 12, and the SiO₂ layer 13 can be suppressed to improve reliability of memory characteristics.

3. The gas layers 18 a, 18 b, 18 c, and 18 d are insulating layers that do not have a trap level. Therefore, degradation of data retention characteristics caused by charge injection from the doped Si layers 14 a 1, 14 a 2, and 14 an functioning as word lines to the Si₃N₄ layer 12 a functions as a data charge storage insulating layer through the trap level does not occur.

4. Upper portions of the gas layers 18 a, 18 b, 18 c, and 18 d are sealed with the TiN layer 16 aa formed by the heat treatment in FIGS. 2GA to 2GC, and the Si pillars 4 a, 4 b, 4 c, and 4 d are supported by the TiN layer 16 aa. With this structure, it is possible to prevent the occurrence of contamination defects due to a phenomenon in which, in a subsequent cleaning treatment step, lithography step, etc., a treatment liquid enters the gas layers 18 a, 18 b, 18 c, and 18 d, remains in the layers, and is not removed. Furthermore, with this structure, the occurrence of tilting or bending of the Si pillars 4 a, 4 b, 4 c, and 4 d can be prevented. In place of the TiN layer 16 a, a laminate including a poly-Si layer and, for example, nickel (Ni) may be used. As a result of heat treatment, Ni atoms diffuse in the poly-Si layer to form a nickel silicide (NiSi) layer. As a result of the heat treatment, the volume of this NiSi layer becomes larger than that of the original poly-Si layer. In this case, since the SiO₂ layer 17 a functioning as a cap layer is disposed on the NiSi, the NiSi layer mainly expands in the horizontal direction of the figure. Consequently, as in the case of the TiN layer 16 aa, upper portions of the gas layers 18 a, 18 b, 18 c, and 18 d are sealed.

Second Embodiment

A method for producing a vertical NAND-type flash memory device according to a second embodiment of the present invention will be described with reference to FIGS. 3A to 3C. The method according to the second embodiment is the same as that of the first embodiment except for a step illustrated with reference to FIGS. 3A to 3C.

As illustrated in FIGS. 3A to 3C, as in FIGS. 2FA to 2FC, atoms of a Si material that contains a donor or acceptor impurity and atoms of a SiO₂ material are incident from a direction perpendicular to an upper surface of an i-layer substrate 1 a by using, for example, a bias sputtering method to form doped Si layers 14 a 1, 14 a 2, and 14 an and SiO₂ layers 15 a 1, 15 a 2, and 15 an on outer peripheries of Si pillars 4 a, 4 b, 4 c, and 4 d. Subsequently, heat treatment is performed, for example, at 450° C. in an atmosphere containing hydrogen (H₂). This heat treatment is performed in a state in which hydrogen gas fills spaces from upper portions to bottom portions of gas layers 18 a, 18 b, 18 c, and 18 d. Subsequently, the steps illustrated in FIGS. 2GA to 2KC are performed.

According to the second embodiment, heat treatment is performed in a state in which hydrogen gas fills spaces from the upper portions to the bottom portions of the gas layers 18 a, 18 b, 18 c, and 18 d. Therefore, hydrogen ions easily diffuse in a SiO₂ layer 13 functioning as an interlayer insulating layer, and uncombined hands (dangling bonds) in the SiO₂ layer 13 are inactivated. Consequently, insulating properties of the SiO₂ layer 13 improve, and reliability of memory characteristics is improved. When a laminate including a poly-Si layer and, for example, nickel (Ni) is used instead of the TiN layer 16 a, heat treatment in a hydrogen environment can be performed at a higher temperature, and thus reliability of memory characteristics further improves. Alternatively, when heat treatment in a hydrogen environment is performed before the formation of the TiN layer 16 a, heat treatment in a hydrogen environment can be performed at a higher temperature, and thus reliability of memory characteristics further improves.

Third Embodiment

A method for producing a vertical NAND-type flash memory device according to a third embodiment of the present invention will be described with reference to FIGS. 4AA to 4BC. The method according to the third embodiment is the same as that of the first embodiment except for steps illustrated with reference to FIGS. 4AA to 4BC.

As illustrated in FIGS. 4AA to 4AC, atoms of a Si material that contains a donor or acceptor impurity and atoms of a SiO₂ material are incident from a direction perpendicular to a surface of an i-layer substrate 1 a by using, for example, a bias sputtering method to form doped Si layers 14 a 1, 14 a 2, and 14 an and SiO₂ layers 15 a 1, 15 a 2, and 15 an on outer peripheries of Si pillars 4 a, 4 b, 4 c, and 4 d. Doped Si layers 14 b 1, 14 b 2, 14 bn, 14 c 1, 14 c 2, 14 cn, 14 d 1, 14 d 2, 14 dn, 14 e 1, 14 e 2, and 14 en, and SiO₂ layers 15 b 1, 15 b 2, 15 bn, 15 c 1, 15 c 2, 15 cn, 15 d 1, 15 d 2, 15 dn, 15 e 1, 15 e 2, and 15 en are stacked on the Si pillars 4 a, 4 b, 4 c, and 4 d, respectively. Subsequently, for example, in an atmosphere containing oxygen at 900° C., a SiO₂ layer 35 a is formed in a surface layer of side faces of the doped Si layers 14 a 1, 14 a 2, and 14 an. At the same time, a SiO₂ layer 35 b is formed in a surface layer of sides of the doped Si layers 14 b 1, 14 b 2, 14 bn, 14 c 1, 14 c 2, 14 cn, 14 d 1, 14 d 2, 14 dn, 14 e 1, 14 e 2, and 14 en.

Next, as illustrated in FIGS. 4BA to 4BC, a TiN layer 16 a and a SiO₂ layer 17 a are formed on the outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d by using a bias sputtering method, and at the same time, TiN layers 16 b, 16 c, 16 d, and 16 e (the TiN layer 16 d is not shown in the figures), and SiO₂ layers 17 b, 17 c, 17 d, and 17 e are stacked on the Si pillars 4 a, 4 b, 4 c, and 4 d, respectively. Subsequently, the steps illustrated in FIGS. 2GA to 2KC are performed. Thus, a vertical NAND-type flash memory device is formed.

According to the third embodiment, the SiO₂ layer 35 a functioning as an interlayer insulating layer is formed in a surface layer of side faces of the doped Si layers 14 a 1, 14 a 2, and 14 an functioning as word lines. Therefore, insulating properties between the Si₃N₄ layer 12 a functions as a data charge storage insulating layer and the doped Si layers 14 a 1, 14 a 2, and 14 an functioning as word lines improve, and reliability of memory characteristics is improved.

Fourth Embodiment

A method for producing a vertical NAND-type flash memory device according to a fourth embodiment of the present invention will be described with reference to FIGS. 5AA to 5CC. In the fourth embodiment, the shape of a material layer deposited by a bias sputtering method will also be described.

FIGS. 5AA to 5AD illustrate a change with time in a material layer deposited on a truncated cone-shaped pillar 37 formed on a substrate 36, and on the substrate 36 in the periphery of the truncated cone-shaped pillar 37, when ionic atoms are incident from a direction perpendicular to a surface of the substrate 36 using a bias sputtering method (refer to, for example, C. Y. Ting, V. J. Vivalda, and H. G. Schaefer: “Study of planarized sputter-deposited SiO₂”, J. Vac. Sci. Technol. 15(3), p.p. 1105-1112, May/June (1978), and A. D. G. Stewart, and M. W. Thomson: “Microtopography of Surface Eroded by Ion-Bombardment, Journal of Material Science 4” p.p. 56-69 (1969)).

It is assumed that, on a truncated cone-shaped pillar 37 which is illustrated in FIG. 5AB and whose inclination angle formed by a substrate 36 and a side face thereof is α (°), ionic atoms are incident from a direction perpendicular to a surface of the substrate 36. In this case, the relationship between the inclination angle α of the side face of the truncated cone-shaped pillar 37 and a deposition rate of an incident ionic atom material layer on the side face of the truncated cone-shaped pillar 37, and the relationship between the inclination angle α and a removal rate of the incident ionic atom material layer will be described with reference to FIGS. 5AA to 5AD. The deposition rate depends on the voltage applied between an anode and a cathode in a bias sputtering apparatus and does not depend on the inclination angle α. With an increase in the voltage applied, the deposition rate increases. On the other hand, as illustrated in FIG. 5AA, with an increase in the inclination angle α, the removal rate increases, becomes maximum at an inclination angle α=θp, and then decreases. Here, the angle θp is 70° or more and 80° or less. The reason why the removal rate increases with an increase in the inclination angle α in this manner is as follows. With an increase in the inclination angle α, the length of a path through which an ionic atom enters a material layer that has already been deposited increases. In this increased entry path, the opportunity of collision between incident ionic atoms and atoms of the deposited material layer increases, and thus a larger number of atoms of the deposited material layer are released. In contrast, when the inclination angle α exceeds θp, it becomes difficult for ionic atoms to enter a material layer that has already been deposited, and a larger number of ionic atoms are reflected at a surface of the deposited material layer. Thus, the opportunity of collision between incident ionic atoms and atoms of the deposited material layer decreases, and the removal rate decreases. As illustrated in FIG. 5AA, in the case of a deposition rate of A-A′, the deposition rate is higher than the removal rate without depending on the inclination angle α. In the case of a deposition rate of B-B′, at an inclination angle α (α<θa) which is smaller than an inclination angle θa at which the deposition rate is equal to the removal rate, the deposition rate is higher than the removal rate, and at an inclination angle α (α>θa) which is larger than the inclination angle θa, the removal rate is higher than the deposition rate. In the case of a deposition rate of C-C′, at almost all inclination angles α, the removal rate is higher than the deposition rate. As illustrated in FIG. 5AC, under a condition in which the deposition rate is higher than the removal rate, deposited material layers 38 a 1, 38 a 2, and 38 a 3 deposited on a truncated cone-shaped pillar 37 and on a substrate 36 located on the outer periphery of the truncated cone-shaped pillar 37 are formed on the substrate 36 and on side faces and a top surface of the truncated cone-shaped pillar 37 in a continuous manner with the lapse of time t0 (before the start of deposition), t1, t2, and t3. In contrast, as illustrated in FIG. 5AD, under a condition in which the deposition rate is lower than the removal rate, since the removal rate on the side faces is high, deposited material layers 39 a 1, 39 a 2, and 39 a 3 deposited on the substrate 36 and deposited material layers 39 b 1, 39 b 2, and 39 b 3 deposited on the truncated cone-shaped pillar 37 are formed to be separated from each other. In this manner, by variously changing the inclination angle α of a side face of the truncated cone-shaped pillar 37 and changing the setting of the deposition rate, the shape of a material layer deposited on the top surface of the truncated cone-shaped pillar 37 and on side faces thereof can be changed.

A method for producing a vertical NAND-type flash memory device according to the fourth embodiment will be described with reference to FIGS. 5BA to 5CC. The method according to the fourth embodiment is the same as that of the first embodiment except for steps illustrated with reference to FIGS. 5BA to 5CC.

As illustrated in FIGS. 5BA to 5BC, truncated cone-shaped Si₃N₄ layers 2A, 2B, 2C, and 2D having a side face with an inclination angle of f3 are formed instead of the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d that are formed on the Si pillars 4 a, 4 b, 4 c, and 4 d, respectively, and illustrated in FIGS. 2EA to 2EC. Subsequently, SiO₂ layers 11 a, 11 b, 11 c, and 11 d (the SiO₂ layer 11 c is not shown in the figures) which are to become tunnel insulating layers are formed in surface layers of side faces of Si pillars 4 a, 4 b, 4 c, and 4 d. A Si₃N₄ layer 12 which is to become a data charge storage insulating layer and a SiO₂ layer 13 which is to become an interlayer insulating layer are further formed so as to cover the whole.

Next, as illustrated in FIGS. 5CA to 5CC, atoms of a Si material that contains a donor or acceptor impurity and atoms of a SiO₂ material are incident from a direction perpendicular to a surface of an i-layer substrate 1 a by using, for example, a bias sputtering method under a condition in which the deposition rate is lower than the removal rate with respect to the inclination angle β of the truncated cone-shaped Si₃N₄ layers 2A, 2B, 2C, and 2D as illustrated in FIG. 5AD. Consequently, doped Si layers 14 a 1, 14 a 2, and 14 an and SiO₂ layers 15 a 1, 15 a 2, and 15 an are formed on outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d, and a TiN layer 16 a and a SiO₂ layer 17 a are further formed thereon. At the same time, truncated cone-shaped stacked material layers 41 a, 41 b, 41 c, and 41 d each having a truncated cone shape and including doped Si layers and SiO₂ layers that form a laminated structure are formed on the Si pillars 4 a, 4 b, 4 c, and 4 d, respectively. After the shape of each of the truncated cone-shaped stacked material layers 41 a, 41 b, 41 c, and 41 d becomes a conical shape, the incident Si material and SiO₂ material are no longer deposited on the truncated cone-shaped stacked material layers 41 a, 41 b, 41 c, and 41 d. Accordingly, a height Lb of each of the truncated cone-shaped stacked material layers 41 a, 41 b, 41 c, and 41 d is smaller than a thickness La that is the total of the thicknesses of the doped Si layers 14 a 1, 14 a 2, and 14 an and the SiO₂ layers 15 a 1, 15 a 2, and 15 an, all of which are formed on the outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d. Subsequently, the steps illustrated in FIGS. 2GA to 2KC are performed.

In the first embodiment, the doped Si layers 14 b 1, 14 b 2, 14 bn, 14 c 1, 14 c 2, 14 cn, 14 d 1, 14 d 2, 14 dn, 14 e 1, 14 e 2, and 14 en, the SiO₂ layers 15 b 1, 15 b 2, 15 bn, 15 c 1, 15 c 2, 15 cn, 15 d 1, 15 d 2, 15 dn, 15 e 1, 15 e 2, and 15 en, the TiN layers 16 bb, 16 cc, 16 dd, and 16 ee, and the SiO₂ layers 17 b, 17 c, 17 d, and 17 e that have the same thickness as the thickness La of the total of the doped Si layers 14 a 1, 14 a 2, and 14 an, the SiO₂ layers 15 a 1, 15 a 2, and 15 an, the TiN layer 16 a, and the SiO₂ layer 17 a are formed on the Si pillars 4 a, 4 b, 4 c, and 4 d, respectively. In this case, defects such as falling and bending of the doped Si layers 14 b 1, 14 b 2, 14 bn, 14 c 1, 14 c 2, 14 cn, 14 d 1, 14 d 2, 14 dn, 14 e 1, 14 e 2, and 14 en, the SiO₂ layers 15 b 1, 15 b 2, 15 bn, 15 c 1, 15 c 2, 15 cn, 15 d 1, 15 d 2, 15 dn, 15 e 1, 15 e 2, and 15 en, the TiN layers 16 bb, 16 cc, 16 dd, and 16 ee, and the SiO₂ layers 17 b, 17 c, 17 d, and 17 e are easily generated by a subsequent cleaning step and the like. In contrast, according to the fourth embodiment, the height Lb of each of the truncated cone-shaped stacked material layers 41 a, 41 b, 41 c, and 41 d is smaller than the thickness La of the total of the doped Si layers 14 a 1, 14 a 2, and 14 an and the SiO₂ layers 15 a 1, 15 a 2, and 15 an, all of which are formed on the outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d. Accordingly, the occurrence of defects such as falling and bending of the truncated cone-shaped stacked material layers 41 a, 41 b, 41 c, and 41 d in a subsequent cleaning step and the like can be prevented.

Fifth Embodiment

A method for producing a vertical NAND-type flash memory device according to a fifth embodiment of the present invention will be described with reference to FIGS. 6A to 6C. The method according to the fifth embodiment is the same as that of the first embodiment except for a step illustrated in FIGS. 6A to 6C.

As illustrated in FIGS. 6A to 6C, truncated cone-shaped Si pillars 4 aa, 4 bb, 4 cc, and 4 dd having a truncated cone shape are respectively formed instead of the Si pillars 4 a, 4 b, 4 c, and 4 d each having a side face perpendicular to a surface of the i-layer substrate 1 a. In each of the truncated cone-shaped Si pillars 4 aa, 4 bb, 4 cc, and 4 dd, the diameter of a bottom portion is larger than the diameter of a top portion. Next, SiO₂ layers 11 a, 11 b, 11 c, and 11 d (the SiO₂ layer 11 c is not shown in the figures) which are to become tunnel insulating layers are formed by, for example, a thermal oxidation method in surface layers of the side faces of the truncated cone-shaped Si pillars 4 aa, 4 bb, 4 cc, and 4 dd. A Si₃N₄ layer 12 functioning as a data charge storage insulating layer and a SiO₂ layer 13 functioning as an interlayer insulating layer are formed so as to cover the whole. In this embodiment, the device is formed so that a diameter Lc of a bottom outer peripheral circle of the SiO₂ layer 13 formed on the peripheries of the bottom of the truncated cone-shaped Si pillars 4 aa, 4 bb, 4 cc, and 4 dd is smaller than a diameter Ld of a side-face outer peripheral circle of the SiO₂ layer 13 formed on the peripheries of the side faces of Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d.

Atoms of a Si material that contains a donor or acceptor impurity and atoms of a SiO₂ material are incident from a direction perpendicular to an upper surface of the i-layer substrate 1 a by using a bias sputtering method to form doped Si layers 14 a 1, 14 a 2, and 14 an, and SiO₂ layers 15 a 1, 15 a 2, and 15 an on outer peripheries of the truncated cone-shaped Si pillars 4 aa, 4 bb, 4 cc, and 4 dd. Subsequently, a TiN layer 16 a and a SiO₂ layer 17 a are formed on the outer peripheries of the truncated cone-shaped Si pillars 4 aa, 4 bb, 4 cc, and 4 dd. In the fifth embodiment, as in the gas layers (spaces) 18 a, 18 b, 18 c, and 18 d of the first embodiment, gas layers (spaces) are formed between the side faces of the truncated cone-shaped Si pillars 4 aa, 4 bb, 4 cc, and 4 dd and the side faces of the doped Si layers 14 a 1, 14 a 2, and 14 an, the SiO₂ layers 15 a 1, 15 a 2, and 15 an, the TiN layer 16 a, and the SiO₂ layer 17 a. With this structure, according to the fifth embodiment, the effects the same as those in the first embodiment are obtained. The shape of each of the Si pillars 4 aa, 4 bb, 4 cc, and 4 dd may not necessarily be a truncated cone shape as described above. The Si pillars may be barrel-shaped Si pillars in which the maximum diameter in a side-face outer peripheral circle of the SiO₂ layer 13 formed on the outer peripheries of the Si pillars 4 aa, 4 bb, 4 cc, and 4 dd is smaller than the diameter of the side-face outer peripheral circle of the SiO₂ layer 13 formed on the outer peripheries of the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d. Also in this case, the effects the same as those in the first embodiment are obtained. In FIGS. 6A to 6C, outer peripheral edges of the Si pillars 4 aa, 4 bb, 4 cc, and 4 dd are respectively located inside outer peripheral edges of gas layers 18 a, 18 b, 18 c, and 18 d in plan view.

Sixth Embodiment

A method for producing a vertical NAND-type flash memory device according to a sixth embodiment of the present invention will be described with reference to FIGS. 7AA to 7HB. In FIGS. 7AA to 7HB, the drawings whose last reference character is A are plan views, and the drawings whose last reference character is B are sectional structural views taken along line X-X′ in the drawings whose last reference character is A. Si pillars 4 a and 4 b correspond to the Si pillars 4 a and 4 b in FIGS. 2BA to 2KC.

As illustrated in FIGS. 7AA and 7AB, on an outer periphery of a memory element region 42 in which the Si pillars 4 a and 4 b are formed, outer peripheral i-layers 43 a and 43 b (the outer peripheral i-layers 43 a and 43 b are connected to each other in the outer periphery of the memory element region 42) which are inclined at an inclination angle θk with respect to an i-layer substrate 1 a are formed. Subsequently, the steps illustrated in FIGS. 2CA to 2HC are performed to form an N⁺ layer 5 a, SiO₂ layers 9, 6 a, and 6 b, a doped Si layer 7, SiO₂ layers 11 aa and 11 bb, a Si₃N₄ layer 12 a, a SiO₂ layer 13 a, doped Si layers 14 a 1, 14 a 2, and 14 an, SiO₂ layers 15 a 1, 15 a 2, and 15 an, and a TiN layer 16 aa. Silicon nitride (Si₃N₄) layers 2 a and 2 b are left on the Si pillars 4 a and 4 b, respectively. The SiO₂ layer 9, the doped Si layer 7, the doped Si layers 14 a 1, 14 a 2, and 14 an, the SiO₂ layers 15 a 1, 15 a 2, and 15 an, and the TiN layer 16 a are formed using, for example, a bias sputtering method by allowing material atoms to be incident from a direction perpendicular to an upper surface of the i-layer substrate 1 a. The deposition of each of the layers by the bias sputtering method is performed under the condition in which the deposition rate is higher than the removal rate at the inclination angle θk of the outer peripheral i-layers 43 a and 43 b, as described with reference to FIG. 5AC. The SiO₂ layers 11 aa and 11 bb, the Si₃N₄ layer 12 a, and the SiO₂ layer 13 a are formed by using an atomic layer deposition (ALD) method. Consequently, the SiO₂ layer 9, the doped Si layer 7, the Si₃N₄ layer 12 a, the SiO₂ layer 13 a, the doped Si layers 14 a 1, 14 a 2, and 14 an, the SiO₂ layers 15 a 1, 15 a 2, and 15 an are formed in a continuous manner on the outer peripheral i-layers 43 a and 43 b in outer peripheries of gas layers (spaces) 18 a, 18 b on outer peripheries of the Si pillars 4 a and 4 b. The TiN layer 16 aa is formed by allowing TiN material atoms to be incident from a direction perpendicular to an upper surface of the i-layer substrate 1 a using, for example, a bias sputtering method, and subsequently, for example, performing heat treatment at 550° C. to cause plastic deformation for extending the deposited TiN layer in the horizontal direction. The TiN layer 16 aa is formed to be in contact with the SiO₂ layer 13 a and to extend on the outer peripheral i-layers 43 a and 43 b in a continuous manner.

Next, as illustrated in FIGS. 7BA and 7BB, the doped Si layer 7, the Si₃N₄ layer 12 a, the SiO₂ layer 13 a, the doped Si layers 14 a 1, 14 a 2, and 14 an, the SiO₂ layers 15 a 1, 15 a 2, and 15 an, and the TiN layer 16 aa that include the Si pillars 4 a and 4 b and extend between the Si pillars 4 a and 4 b and over the outer peripheral i-layer 43 b in a continuous manner are formed by using a lithographic method and an RIE method.

Next, as illustrated in FIGS. 7CA and 7CB, SiO₂ is deposited by a CVD method. The resulting SiO₂ layer is then planarized by a chemical mechanical polishing (CMP) method to form a SiO₂ layer 45 whose surface is located higher than an upper surface of the TiN layer 16 aa on the outer peripheral i-layer 43 b.

Next, as illustrated in FIGS. 7DA and 7DB, the SiO₂ layer 45, the doped Si layer 7, the Si₃N₄ layer 12 a, the SiO₂ layer 13 a, the doped Si layers 14 a 1, 14 a 2, and 14 an, the SiO₂ layers 15 a 1, 15 a 2, and 15 an, and the TiN layer 16 aa are etched using a CMP method such that an upper surface thereof has a height substantially equal to that of an upper surface of the SiO₂ layer 9 on the outer peripheral i-layers 43 a and 43 b.

Next, as illustrated in FIGS. 7EA and 7EB, a Si₃N₄ layer 46 which is an insulating layer is formed on the doped Si layer 7, the Si₃N₄ layer 12 a, the SiO₂ layer 13 a, the doped Si layers 14 a 1, 14 a 2, and 14 an, the SiO₂ layers 15 a 1, 15 a 2, and 15 an, and the TiN layer 16 aa whose upper surfaces are exposed on the outer peripheral i-layer 43 b. Subsequently, the SiO₂ layer 9 is etched by using a lithographic method and an RIE method to form SiO₂ layers 47 a and 47 b. Subsequently, the outer peripheral i-layer 43 a is etched by using, for example, an RIE method using the SiO₂ layers 47 a and 47 b as a mask to form Si pillars 48 a and 48 b, respectively, such that bottom surfaces of the Si pillars 48 a and 48 b have a height substantially equal to that of the upper surface of the TiN layer 16 aa. Subsequently, the SiO₂ layers 45 and 9 on the memory element region 42 are etched by using, for example, an etch-back method such that the upper surfaces thereof have a height substantially equal to that of the upper surface of the TiN layer 16 aa.

Next, as illustrated in FIGS. 7FA and 7FB, a P⁺ layer 51 a is formed in a bottom portion of the Si pillar 48 a by using a lithographic method, an acceptor impurity ion implantation method, and a thermal diffusion method. Similarly, an N⁺ layer 52 a is formed in a bottom portion of the Si pillar 48 b by using a lithographic method, a donor impurity ion implantation method, and a thermal diffusion method. Subsequently, a SiO₂ layer 50 is formed over the outer peripheries of the Si pillars 4 a, 4 b, 48 a, and 48 b. Subsequently, a HfO₂ layer 53 and a TiN layer 54 are deposited by an ALD method over the entire surface so as to cover the Si pillars 4 a, 4 b, 48 a, and 48 b.

Next, as illustrated in FIGS. 7GA and 7GB, the TiN layer 54 is etched by using a lithographic method and an RIE method to form a TiN layer 54 a that surrounds the Si pillars 48 a and 48 b and that is connected to the Si pillars 48 a, and 48 b. At the same time, a TiN layer 54 b that surrounds the Si pillars 4 a and 4 b and that is connected to the Si pillars 4 a, and 4 b is formed. Subsequently, parts of the HfO₂ layer 53 and the TiN layers 54 a and 54 b disposed on top portions of the Si pillars 4 a, 4 b, 48 a, and 48 b are removed. Subsequently, by using a lithographic method and an ion implantation method, a P⁺ layer 51 b is formed in a top portion of the Si pillar 48 a, and N⁺ layers 52 b, 55 a, and 55 b are respectively formed in top portions of the Si pillars 48 b, 4 a, and 4 b.

Next, as illustrated in FIGS. 7HA and 7HB, SiO₂ is deposited by a CVD method, and a SiO₂ layer 56 whose surface is smoothly polished is formed by a CMP method such that the surface of the SiO₂ layer 56 is located higher than the upper surface of the outer peripheral i-layer 43 b. Subsequently, a contact hole 57 a is formed on the Si pillar 48 a. A contact hole 57 b is formed on the Si pillar 48 b. A contact hole 57 c is formed on the TiN layer 54 a. A contact hole 57 d is formed on a boundary line between the P layer 51 a and the N⁺ layer 52 a that are formed in a surface layer of the outer peripheral i-layer 43 a. Subsequently, a power supply wiring metal layer Vdd connected to the P⁺ layer 51 b through the contact hole 57 a, a ground wiring metal layer Vss connected to the N⁺ layer 52 b through the contact hole 57 b, an input wiring metal layer Vin connected to the TiN layer 54 a through the contact hole 57 c, and an output wiring metal layer Vout connected to the P⁺ layer 51 a and the N⁺ layer 52 a through the contact hole 57 d are formed. Subsequently, a SiO₂ layer 58 having a smooth surface is formed so as to cover the whole by using a CVD method and a CMP method. Subsequently, a contact hole 59 a is formed on the TiN layer 54 b. A contact hole 59 b is formed on the Si pillar 4 a. A contact hole 59 c is formed on the Si pillar 4 b. A contact hole 59 d is formed on the doped Si layer 14 a 1 extending to the top of the outer peripheral i-layer 43 b. A contact hole 59 e is formed on the doped Si layer 14 a 2 extending to the top of the outer peripheral i-layer 43 b. A contact hole 59 f is formed on the doped Si layer 14 an extending to the top of the outer peripheral i-layer 43 b. Subsequently, a drain-side selection gate wiring metal layer SGD connected to the TiN layer 54 b through the contact hole 59 a, a bit-line wiring metal layer BLa connected to the N⁺ layer 55 a through the contact hole 59 b, a bit-line wiring metal layer BLb connected to the N⁺ layer 55 b through the contact hole 59 c, a word-line wiring metal layer WL1 connected to the doped Si layer 14 a 1 through the contact hole 59 d, a word-line wiring metal layer WL2 connected to the doped Si layer 14 a 2 through the contact hole 59 e, and word-line wiring metal layer WLn connected to the doped Si layer 14 an through the contact hole 59 f are formed. Similarly, the N⁺ layer 5 a is connected to a common source wiring layer, and the doped Si layer 7 is connected to a source-side selection gate wiring layer (the common source wiring layer and the source-side selection gate wiring layer are not shown in the figures).

As illustrated in FIGS. 7HA and 7HB, a P-channel surrounding gate MOS transistor (SGT) and an N-channel SGT are formed on the outer peripheral i-layer 43 a (regarding an SGT, refer to, for example, Japanese Unexamined Patent Application Publication No. 2-188966). In the P-channel SGT, the P⁺ layer 51 a functions as a source, the P⁺ layer 51 b functions as a drain, the Si pillar 48 a disposed between the P⁺ layers 51 a and 51 b functions as a channel, and the TiN layer 54 a functions as a gate. In the N-channel SGT, the N⁺ layer 52 a functions as a source, the N⁺ layer 52 b functions as a drain, the Si pillar 48 b disposed between the N⁺ layers 52 a and 52 b functions as a channel, and the TiN layer 54 a functions as a gate. The P-channel SGT and the N-channel SGT that are respectively formed in the Si pillars 48 a and 48 b form a CMOS inverter circuit. A vertical NAND-type flash memory device, as illustrated in FIG. 1, in which memory cell-transistors are connected in series in n stages is formed around the Si pillars 4 a and 4 b in the memory element region 42.

According to the sixth embodiment, the following advantages are achieved.

1. The P-channel SGT formed in the Si pillar 48 a, the N-channel SGT formed in the Si pillar 48 b, and drain-side selection transistors of the vertical NAND-type flash memory device formed in top portions of the Si pillars 4 a and 4 b are formed so as to have heights that are equal to each other. Accordingly, the HfO₂ layer 53 which is gate insulating layers of the P-channel SGT, the N-channel SGT, and the drain-side selection transistor can be formed at the same time. Similarly, the TiN layer 54 which is gate conductor layers of the P-channel SGT, the N-channel SGT, and the drain-side selection transistor can be formed at the same time. Similarly, the N⁺ layer 52 b of the N-channel SGT, and the N⁺ layers 55 a and 55 b of the vertical NAND-type flash memory device can be formed at the same time. In this manner, many steps necessary for forming a peripheral circuit formed of the P-channel SGT and the N-channel SGT that are disposed on the outer peripheral i-layer 43 a and many steps necessary for forming the drain-side selection transistor of the vertical NAND-type flash memory device can be performed in common. Therefore, a reduction in the cost of the NAND-type flash memory device produced can be realized.

2. In the vertical NAND-type flash memory device, the doped Si layers 14 a 1, 14 a 2, and 14 an functioning as word-line conductor layers and the SiO₂ layers 15 a 1, 15 a 2, and 15 an for insulating the doped Si layers 14 a 1, 14 a 2, and 14 an from each other are formed by allowing material atoms to be incident from a direction perpendicular to a surface of the i-layer substrate 1 a using a bias sputtering method. In the Si pillars 4 a and 4 b, these material layers are deposited by using the Si₃N₄ layers 2 a and 2 b as a mask under the condition in which the deposition rate of the bias sputtering is higher than the removal rate with respect to the inclination angle θk of the outer peripheral i-layers 43 a and 43 b. Accordingly, gas layers (spaces) 18 a and 18 b can be formed on the outer peripheries of the Si pillars 4 a and 4 b, respectively. In addition, the doped Si layers 14 a 1, 14 a 2, and 14 an and the SiO₂ layers 15 a 1, 15 a 2, and 15 an are formed on a side face of the outer peripheral i-layer 43 b in a continuous manner. As a result, the word-line wiring metal layers WL1, WL2, and WLn can be respectively formed through the contact holes 59 d, 59 e, and 59 f, whose bottom surfaces have heights equal to each other. Therefore, the steps of forming the word-line wiring metal layers WL1, WL2, and WLn are simplified to realize a reduction in the production cost of the NAND-type flash memory device.

In the first embodiment, a description has been made of a case in which when a doped Si layer 14 a 1 and a SiO₂ layer 15 a 1 form one set, at least three sets of the doped Si layers 14 a 1, 14 a 2, and 14 an and the SiO₂ layers 15 a 1, 15 a 2, and 15 an are used in a vertical NAND-type flash memory. However, the structure in the first embodiment is applicable to other electrically erasable programmable read only memories (EEPROM) such as a NOR-type memory including one set of the doped Si layer 14 a 1 and the SiO₂ layer 15 a 1. This is also similarly applicable to other embodiments of the present invention.

In the first embodiment, atoms of a Si material that contains a donor or acceptor impurity and atoms of a SiO₂ material are incident from a direction perpendicular to an upper surface of the i-layer substrate 1 a by using a bias sputtering method to form the doped Si layers 14 a 1, 14 a 2, and 14 an and the SiO₂ layers 15 a 1, 15 a 2, and 15 an on outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d. Alternatively, other methods may be used as long as the doped Si layers 14 a 1, 14 a 2, and 14 an and the SiO₂ layers 15 a 1, 15 a 2, and 15 an can be formed by allowing a Si material that contains a donor or acceptor impurity and a SiO₂ material to be incident from a direction perpendicular to an upper surface of the i-layer substrate 1 a. This is also similarly applicable to other embodiments of the present invention.

The doped Si layers 14 a 1, 14 a 2, and 14 an in the first embodiment may be formed of amorphous silicon or polysilicon. This is also similarly applicable to other embodiments of the present invention.

The doped Si layers 14 a 1, 14 a 2, and 14 an in the first embodiment may be layers formed of a material having electrical conductivity. This is also similarly applicable to other embodiments of the present invention.

The SiO₂ layers 11 aa, 11 bb, 11 cc, and 11 dd functioning as tunnel insulating layers, the Si₃N₄ layer 12 a functioning as a data charge storage insulating layer, and the SiO₂ layer 13 a functioning as an interlayer insulating layer in the first embodiment may be layers formed of other materials as long as the layers can achieve the functions of the respective layers. This is also similarly applicable to other embodiments of the present invention.

In the first embodiment, the TiN layer 16 a or a laminate including a poly-Si layer and nickel (Ni) is used. The TiN layer 16 a or a NiSi layer expands in the horizontal direction of the drawing as a result of plastic deformation or volume expansion caused by heat treatment, so that the upper portions of the gas layers (spaces) 18 a, 18 b, 18 c, and 18 d are sealed. Alternatively, a layer formed of other materials may be used as long as the upper portions of the gas layers 18 a, 18 b, 18 c, and 18 d are sealed as in the case where such a TiN layer or a NiSi layer is used. This is also similarly applicable to other embodiments of the present invention.

In the description of the first embodiment, the doped Si layer 7 is used as an example of the source-side selection gate wiring metal layer (conductor layer) and the doped Si layer 20 a is used as an example of the drain-side selection gate wiring metal layer (conductor layer). However, the layers are not limited thereto. Alternatively, conductor layers formed of other materials may be used. This is also similarly applicable to other embodiments of the present invention.

In the first embodiment, a NAND-type flash memory device is formed around the Si pillars 4 a, 4 b, 4 c, and 4 d. However, the structure is not limited thereto. The NAND-type flash memory device may be formed around other semiconductor pillars. This is also similarly applicable to other embodiments of the present invention.

In the first embodiment, a Si₃N₄ layer is etched by using, as a mask, resist layers 3 a, 3 b, 3 c, and 3 d each having a perfect circular shape using, for example, a reactive ion etching (RIE) method to form the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d, respectively. However, the shapes of these layers are not limited thereto. The shapes of the resist layers 3 a, 3 b, 3 c, and 3 d and the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d in plan view may be, for example, an ellipse. This is also similarly applicable to other embodiments of the present invention.

In the first embodiment, the i-layer substrate 1 is etched by using, as a mask, the resist layers 3 a, 3 b, 3 c, and 3 d and the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d using, for example, an RIE method to form the Si pillars 4 a, 4 b, 4 c, and 4 d, respectively. However, the method is not limited thereto. The i-layer substrate 1 may be etched by using the resist layers 3 a, 3 b, 3 c, and 3 d or the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d without using all the resist layers 3 a, 3 b, 3 c, and 3 d and the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d. Alternatively, layers formed of other materials may be used as long as the layers can achieve the functions of the resist layers 3 a, 3 b, 3 c, and 3 d and the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d. This is also similarly applicable to other embodiments of the present invention.

In the first embodiment, the doped Si layers 14 a 1, 14 a 2, and 14 an which are to become word lines, and the doped Si layer 7 which is to become a source-side selection line have been described using a structure in which these layers are formed on outer peripheries of the Si pillars 4 a, 4 b, 4 c, and 4 d in a continuous manner. However, the structure is not limited thereto. In accordance with the specification of the device operation, as in the structure of the doped Si layers 20 a and 20 b which are to become drain-side selection lines, the doped Si layers 14 a 1, 14 a 2, and 14 an and the doped Si layer 7 may have a separated structure including doped Si layers formed on outer peripheries of the Si pillars 4 a and 4 b in a continuous manner and doped Si layers formed on outer peripheries of the Si pillars 4 c and 4 d in a continuous manner. This structure is also within the technical idea of the present invention. This is also similarly applicable to other embodiments of the present invention.

In the first embodiment, a description has been made using a structure in which the Si pillars 4 a, 4 b, 4 c, and 4 d have the N⁺ layer 5 a functioning as a common source in a bottom portion thereof and the N⁺ layers 24 a, 24 b, 24 c, and 24 d functioning as drains in top portions thereof. The technical idea of the present invention is also applicable to a vertical NAND-type flash memory device (refer to, for example, the specification of U.S. Pat. No. 8,189,371) in which two Si pillars form a single NAND-type flash memory device. In this case, the common source N⁺ layer 5 a and the drain N⁺ layers 24 a, 24 b, 24 c, and 24 d are formed in top portions of the Si pillars 4 a, 4 b, 4 c, and 4 d. The channels of the NAND-type flash memory device include a channel of a Si pillar connected to the common source N⁺ layer and a channel of a Si pillar connected to one drain N⁺ layer connected to the channel. This is also similarly applicable to other embodiments of the present invention.

The hydrogen heat treatment in the second embodiment has been described using the first embodiment as an example. This is also similarly applicable to other embodiments of the present invention.

The content described in the fourth embodiment is also applicable to other embodiments of the present invention.

In the fourth embodiment, the truncated cone-shaped Si₃N₄ layers 2A, 2B, 2C, and 2D are formed instead of the Si₃N₄ layers 2 a, 2 b, 2 c, and 2 d. The truncated cone-shaped stacked material layers 41 a, 41 b, 41 c, and 41 d are formed on the truncated cone-shaped Si₃N₄ layers 2A, 2B, 2C, and 2D, respectively. The shape of each of the truncated cone-shaped stacked material layers 41 a, 41 b, 41 c, and 41 d is not limited to such a truncated cone shape but may be any tapered shape. This is also similarly applicable to other embodiments of the present invention.

In the sixth embodiment, the Si pillars 48 a and 48 b are formed such that the bottom surfaces of the Si pillars 48 a and 48 b have a height substantially equal to that of the upper surface of the TiN layer 16 aa. However, the structure is not limited thereto. The height of the bottom surfaces of the Si pillars 48 a and 48 b may be in the vicinity of the height of the surface of the TiN layer 16 aa as long as the SGTs are formed in the Si pillars 48 a and 48 b.

In the sixth embodiment, a single-layered TiN layer 54 is used. However, the layer is not limited thereto. Instead of the single-layered TiN layer 54, for example, a layer having a two-layer structure including a poly-Si layer, or a layer formed of another material may also be used.

In the sixth embodiment, the contact holes 59 d, 59 e, and 59 f are formed in the vicinity of the center line X-X′ of the Si pillars 4 a and 4 b in which a NAND-type flash memory device is formed. However, the structure is not limited thereto. Since the doped Si layers 14 a 1, 14 a 2, and 14 an are formed over the entire memory element region 42 in a continuous manner, the contact holes 59 d, 59 e, and 59 f need not be necessarily formed so as to gather in the vicinity of the line X-X′ as illustrated in FIGS. 7HA and 7HB.

In the sixth embodiment, a description has been made of an example in which a CMOS inverter circuit including the P-channel SGT and the N-channel SGT is formed in the Si pillars 48 a and 48 b on the outer peripheral i-layer 43 a. Also in the case where a circuit using other SGTs is formed, the technical idea of the present invention is applicable.

According to the present invention, a pillar-shaped semiconductor memory device having a high density and a low cost, and a high-performance, new-function electronic device using the memory device can be provided. 

What is claimed is:
 1. A pillar-shaped semiconductor memory device comprising: a semiconductor substrate; a first semiconductor pillar disposed on the semiconductor substrate and extending in a direction perpendicular to a surface of the semiconductor substrate; a tunnel insulating layer surrounding an outer periphery of the first semiconductor pillar; a data charge storage insulating layer surrounding an outer periphery of the tunnel insulating layer; a first interlayer insulating layer surrounding an outer periphery of the data charge storage insulating layer; a space surrounding an outer periphery of the first interlayer insulating layer; at least one stacked material layer that surrounds an outer periphery of the space and that is formed in a direction perpendicular to the surface of the semiconductor substrate, the stacked material layer including a first conductor layer and a second interlayer insulating layer; and a second conductor layer that is formed on the outer periphery of the first semiconductor pillar and on the at least one stacked material layer, that supports a side face of the first interlayer insulating layer, and that seals the space, wherein the first interlayer insulating layer and the space insulate the first conductor layer from the data charge storage insulating layer, the first interlayer insulating layer insulates the second conductor layer from the data charge storage insulating layer, and data writing and erasing due to data charge transfer between the first semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer or data charge retention by the data charge storage insulating layer is performed by application of a voltage to the first conductor layer.
 2. The pillar-shaped semiconductor memory device according to claim 1, wherein the at least one stacked material layer comprises a plurality of stacked material layers, the pillar-shaped semiconductor memory device further includes a first gate insulating layer formed below the stacked material layers and surrounding the outer periphery of the first semiconductor pillar, a third conductor layer surrounding an outer periphery of the first gate insulating layer, a first impurity region formed below the third conductor layer and in a bottom portion of the first semiconductor pillar and containing a donor or acceptor impurity, a second gate insulating layer formed above the stacked material layers and surrounding the outer periphery of the first semiconductor pillar, a fourth conductor layer surrounding an outer periphery of the second gate insulating layer, and a second impurity region formed in a top portion of the first semiconductor pillar and having the same conductivity type as the first impurity region, and the first conductor layer of each of the stacked material layers is connected to a word-line wiring metal layer, the third conductor layer is connected to a source-side selection gate wiring metal layer, the first impurity region is connected to a common source wiring metal layer, the fourth conductor layer is connected to a drain-side selection gate wiring metal layer, and the second impurity region is connected to a bit-line wiring metal layer to form a NAND-type flash memory element in the first semiconductor pillar.
 3. The pillar-shaped semiconductor memory device according to claim 1, wherein an outer peripheral edge of the first semiconductor pillar is disposed inside an outer peripheral edge of the space in plan view.
 4. The pillar-shaped semiconductor memory device according to claim 2, further comprising: a first outer peripheral semiconductor region formed in an outer periphery of a memory element region in which the first semiconductor pillar is formed; a second semiconductor pillar which is formed in a second outer peripheral semiconductor region included in the first outer peripheral semiconductor region, whose top portion has a height substantially equal to that of a top portion of the first semiconductor pillar, and whose bottom surface has a height substantially equal to that of a bottom surface of the fourth conductor layer; a third gate insulating layer surrounding an outer periphery of the second semiconductor pillar; a fifth conductor layer which is formed so as to surround an outer periphery of the third gate insulating layer, and whose upper and lower ends have heights substantially equal to those of upper and lower ends of the fourth conductor layer; a third impurity region formed above the fifth conductor layer and in a top portion of the second semiconductor pillar and containing a donor or acceptor impurity; and a fourth impurity region formed below the fifth conductor layer and in a bottom portion of the second semiconductor pillar and having the same conductivity type as the third impurity region, wherein a surrounding gate MOS transistor (SGT) is formed in which when one of the third impurity region and the fourth impurity region functions as a source, the other functions as a drain, the second semiconductor pillar disposed between the third impurity region and the fourth impurity region functions as a channel, and the fifth conductor layer functions as a gate.
 5. The pillar-shaped semiconductor memory device according to claim 2, further comprising: a third interlayer insulating layer that is formed on the semiconductor substrate so as to surround the outer periphery of the first semiconductor pillar, and that extends to a side face and an upper surface of the first outer peripheral semiconductor region; and a contact hole connected to an upper surface of the first conductor layer of one of the stacked material layers that have an upper surface on an upper end of a side face of the first outer peripheral semiconductor region, wherein the stacked material layers are formed on the third interlayer insulating layer, an upper surface of the stacked material layers has a height substantially equal to that of an upper surface of the third interlayer insulating layer located on the first outer peripheral semiconductor region, and the first conductor layer and the word-line wiring metal layer are connected to each other through the contact hole.
 6. A method for producing a pillar-shaped semiconductor memory device, the method comprising: a mask insulating layer-forming step of forming, on a semiconductor substrate, a mask insulating layer having a circular shape in plan view; a first semiconductor pillar-forming step of forming a first semiconductor pillar by etching the semiconductor substrate using the mask insulating layer as a mask to form a semiconductor pillar on the semiconductor substrate, and retracting a side face of the semiconductor pillar to the inside of the semiconductor pillar; a tunnel insulating layer-forming step of forming a tunnel insulating layer so as to surround an outer periphery of the first semiconductor pillar; a data charge storage insulating layer-forming step of forming a data charge storage insulating layer so as to surround an outer periphery of the tunnel insulating layer; a first interlayer insulating layer-forming step of forming a first interlayer insulating layer so as to surround an outer periphery of the data charge storage insulating layer; a first conductor layer-forming step of forming a first conductor layer on the outer periphery of the first semiconductor pillar and above the semiconductor substrate by allowing a material atom to be incident from a direction perpendicular to an upper surface of the mask insulating layer; a second interlayer insulating layer-forming step of forming a second interlayer insulating layer by allowing a material atom to be incident on the first conductor layer from a direction perpendicular to the upper surface of the mask insulating layer; a space-forming step of forming a space between a side face of the first interlayer insulating layer and side faces of the first conductor layer and the second interlayer insulating layer in parallel with the first conductor layer-forming step and the second interlayer insulating layer-forming step; and a stacked material layer-forming step of forming at least one stacked material layer in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer as one set, wherein data writing and erasing due to data charge transfer between the first semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer or data charge retention by the data charge storage insulating layer is performed by application of a voltage to the first conductor layer.
 7. The method according to claim 6, further comprising: a second conductor layer-forming step of forming a second conductor layer on the outer periphery of the first semiconductor pillar and on the at least one stacked material layer by allowing a material atom to be incident from a direction perpendicular to the upper surface of the mask insulating layer; and a second conductor layer-first interlayer insulating layer-connecting step of connecting the second conductor layer to the first interlayer insulating layer by expanding the second conductor layer by heat treatment in a direction parallel to the upper surface of the semiconductor substrate.
 8. The method according to claim 7, wherein, between the stacked material layer-forming step and the second conductor layer-first interlayer insulating layer-connecting step, heat treatment is performed in an atmosphere containing hydrogen.
 9. The method according to claim 7, wherein, between the stacked material layer-forming step and the second conductor layer-first interlayer insulating layer-connecting step, heat treatment is performed in an atmosphere containing oxygen to form an oxide insulating layer in a surface layer of a side face of the first conductor layer.
 10. The method according to claim 6, comprising: a truncated cone-shaped mask insulating layer-forming step of forming, as the mask insulating layer, a truncated cone-shaped mask insulating layer having a truncated cone shape on the first semiconductor pillar; and a cone-shaped stacked material layer-forming step of depositing a material atom by allowing the material atom to be incident from a direction perpendicular to the upper surface of the semiconductor substrate under a condition in which a deposition rate of the material atom on a side face of the truncated cone-shaped mask insulating layer is lower than a removal rate of the material atom to form the at least one stacked material layer above the semiconductor substrate and to form, on the truncated cone-shaped mask insulating layer, a cone-shaped stacked material layer having a conical shape and formed of a material layer common to the at least one stacked material layer.
 11. The method according to claim 6, further comprising: a first gate insulating layer-forming step of forming a first gate insulating layer below the at least one stacked material layer so as to surround the outer periphery of the first semiconductor pillar; a third conductor layer-forming step of forming a third conductor layer so as to surround an outer periphery of the first gate insulating layer; a first impurity region-forming step of forming a first impurity region below the third conductor layer and in a bottom portion of the first semiconductor pillar, the first impurity region containing a donor or acceptor impurity; a second gate insulating layer-forming step of forming a second gate insulating layer above the at least one stacked material layer so as to surround the outer periphery of the first semiconductor pillar; a fourth conductor layer-forming step of forming a fourth conductor layer so as to surround an outer periphery of the second gate insulating layer; and a second impurity region-forming step of forming a second impurity region above the fourth conductor layer, the second impurity region having the same conductivity type as the first impurity region, wherein the first conductor layer of the at least one stacked material layer is connected to a word-line wiring metal layer, the third conductor layer is connected to a source-side selection gate wiring metal layer, the first impurity region is connected to a common source wiring metal layer, the fourth conductor layer is connected to a drain-side selection gate wiring metal layer, and the second impurity region is connected to a bit-line wiring metal layer to form a NAND-type flash memory element in the first semiconductor pillar.
 12. The method according to claim 10, further comprising: a first outer peripheral semiconductor region-forming step of forming a first outer peripheral semiconductor region in an outer periphery of a memory element region in which the first semiconductor pillar is formed; a second semiconductor pillar-forming step of forming, in a second outer peripheral semiconductor region included in the first outer peripheral semiconductor region, a second semiconductor pillar whose top portion has a height substantially equal to that of a top portion of the first semiconductor pillar, and whose bottom surface has a height substantially equal to that of a bottom surface of the fourth conductor layer; a third gate insulating layer-forming step of forming a third gate insulating layer so as to surround an outer periphery of the second semiconductor pillar; a fifth conductor layer-forming step of forming a fifth conductor layer whose upper and lower ends have heights substantially equal to those of upper and lower ends of the fourth conductor layer in a direction perpendicular to the semiconductor substrate so as to surround an outer periphery of the third gate insulating layer; a third impurity region-forming step of forming a third impurity region above the fifth conductor layer and in a top portion of the second semiconductor pillar, the third impurity region containing a donor or acceptor impurity; and a fourth impurity region-forming step of forming a fourth impurity region below the fifth conductor layer and in a bottom portion of the second semiconductor pillar, the fourth impurity region having the same conductivity type as the third impurity region, wherein a surrounding gate MOS transistor (SGT) is formed in which when one of the third impurity region and the fourth impurity region functions as a source, the other functions as a drain, the second semiconductor pillar disposed between the third impurity region and the fourth impurity region functions as a channel, and the fifth conductor layer function as a gate.
 13. The method according to claim 10, further comprising: a third interlayer insulating layer-forming step of forming a third interlayer insulating layer on the semiconductor substrate so as to surround the outer periphery of the first semiconductor pillar, the third interlayer insulating layer extending to a side face and an upper surface of the first outer peripheral semiconductor region; and a contact hole-forming step of forming a contact hole so as to be connected to an upper surface of the first conductor layer of the at least one stacked material layer that has an upper surface on an upper end of a side face of the second outer peripheral semiconductor region, wherein the at least one stacked material layer is formed on the third interlayer insulating layer, an upper surface of the at least one stacked material layer has a height substantially equal to that of an upper surface of the third interlayer insulating layer located on the first outer peripheral semiconductor region, and the first conductor layer and the word-line wiring metal layer are connected to each other through the contact hole. 